Design a Decade Counter Using T Flip-flops

dezembro 20, 2021 Postar um comentário

CS302 - Digital Logic & Design

Lesson No. 29

UP/DOWN COUNTER

The down-counter is implemented by connecting the Q 0 and Q 1 outputs. Figure 29.1

F 0

F 1

F 2

SET

flip-flop 1

flip-flop 2

flip-flop 3

CLR

CLK

Figure 29.1

3-bit Synchronous Down-counter

The down-counter counter circuit is very similar to the up-counter circuit discussed

earlier. The only change is the connection of the AND gate to the complementary outputs of

the first and second flip-flops.

The up-counter and down-counter can be implemented as a single counter circuit by adding

some extra logic. In the circuit diagram, the Up-down counter is configured to count up or

down by setting the UP / DOWN input to logic 1 or 0 respectively. When the UP / DOWN

input is set to logic 1, upper AND gates are enabled, allowing flip-flip 2 to toggle its state when

F 0 output of flip-flop 1 is logic 1. Similarly when both F 0 and F 1 outputs are logic 1, flip-flop 3

toggles its state. When the UP / DOWN input is set to logic 0, the lower AND gates are

enabled. When F 0 is logic 0, Q 0 is logic 1 and the flip-flop 2 toggles its output state. Similarly,

when both outputs F 0 and F 1 are at logic 0, that is, Q 0 and Q 1 are at logic 1 the flip-flop 3

toggles its state. During the counting sequence, the UP / DOWN input can be set to logic 1 or

0 at any time to reverse the counting sequence. Figure 29.2

293

CS302 - Digital Logic & Design

F 0

F 1

F 2

UP / DOW N

SET

flip-flop 2

flip-flop 1

flip-flop 3

CLR

CLK

Figure 29.2a Up-Down Synchronous Counter

UP / DOWN

Figure 29.2b Timing diagram of an Up-Down Synchronous Counter

294

CS302 - Digital Logic & Design

Integrated Circuit Up/Down Decade Counter

Implementing a 4-bit Up/Down counter by connecting flip-flops and logic gates

increases the circuit size and requires many connections. The 74HC190 is a 4-bit Up/Down

Synchronous Counter available in an Integrated Circuit form. Figure 29.3. The counter has the

following pins.

Parallel data inputs D 0 , D 1 , D 2 and D 3

Data outputs Q 0 , Q 1 , Q 2 and Q 3

Positive edge-triggered CLOCK signal

Active-low LOAD input which loads the 4-bit data applied at the counter inputs

Active-low CTEN counter enable input

D / U the count down/up input. When the input is set to logic 1, the counter counts down

and when the input is set to logic 0, the counter counts up

7. The MAX/MIN output that is set to high when the terminal count 1001 is reached when

counting up or when the terminal count 0000 is reached when counting down. The

MAX/MIN output is logic high for one complete cycle when a terminal count is reached.

8. The Ripple Clock Output RCO goes low when the Counter reaches the terminal count

1001 or 0000 when counting up or down respectively. The RCO output remains low during

the negative half of the clock cycle. The RCO, the MAX/MIN output along with CTEN input

is used to cascade multiple counter ICs for implementing larger counters.

D 0 D 1 D 2 D 3

CTEN

LOAD

MAX/MIN

74HC190

D/U

RCO

CLK

Q 0 Q 1 Q 2 Q 3

Figure 29.3

74HC190 4-bit Synchronous Up/Down Counter

Counter Decoding

In digital circuits the counter outputs are decoded using decoders or logic gates to

determine when the counter is in a certain state in its counting sequence. For example, a 4-bit

Modulus-16 counter counts from state 0 to state 15. A digital circuit is enabled when the count

reaches count value 4, a second circuit is enabled when the count value reaches 8 and a third

circuit is enabled when the count value reaches 12. A decoder using AND or NAND gates

logic gates can be implemented. Figure 29.4

295

CS302 - Digital Logic & Design

F 1

F 2

F 0

F 3

SET

flip-flop 1

flip-flop 2

flip-flop 3

flip-flop 4

CLR

CLK

Active-high

Active-low

select 4

select 8

select 12

Figure 29.4a Decoder circuit decoding counter outputs 4, 8 and 12

The output of the first AND gate is set to logic high when the counter output is set to

0100 (4). The output of the second AND gate is set to logic high when the counter output is set

to 1000 (8). The NAND gate is set to logic low when the counter output is set to 1100 (12). The

propagation delay due to ripple effect in Asynchronous counters, discussed earlier causes

these Asynchronous counters to work erratically. The propagation problem also exists in

Synchronous counters to some degree due to the propagation delays from the clock transition

to the Q output of the flip-flop which varies slightly for each flip-flop. The timing diagram for the

decoder circuit shows that the decoder outputs are activated for different time intervals at

different intervals which are not in a proper sequence. Figure 29.4b. The counter output for

count 2 is detected by the AND gate decoder during interval t 2A to t 3 and again for a very short

interval at t 4 . Similarly, the counter output 8 is selected for a very short duration between

intervals t AB and t 9 . The decoder outputs for very short durations at interval t 2 , t 4 , t 6 and t 8 are

known as `gliches'.

Glitches can be eliminated by enabling the decoder outputs after the glitches have

settled down. Glitches are removed by using the clock signal to enable the decoder circuit.

Figure 29.5. The clock signal is connected to the inputs of each of the three decoder gates.

During the second, positive half of the clock signal the three gates are enabled, all the glitches

occur during the first negative half of the clock cycle during which the decoder gates are

disabled. This method is known as Strobing method where the decoder outputs are activated

after some delay allowing the glitches to settle down.

296

CS302 - Digital Logic & Design

CLOCK

Input

F 0

Output

F 1

Output

F 2

Output

F 3

Output

20 4

640

t 2 t 2A

t 3

t 4 t 4A t 5

t 6

t 7

t 8 t A8 t 9

t 10

t 1

Figure 29.4b Decoded Outputs of Synchronous Counter

F 1

F 2

F 0

F 3

SET

flip-flop 1

flip-flop 2

flip-flop 3

flip-flop 4

CLR

CLK

Active-high

Active-low

select 4

select 8

select 12

Figure 29.5

The Decoder circuit connected to remove glitches

Glitches occur even with Integrated circuits due to different propagation delays

between the clock transition and the variable path lengths between different inputs and outputs

within the integrated circuit. The Glitches that occur at the output of a 74x 138 3-to-8 decoder

connected to a 74HC163 counter can be removed by enabling the decoder during the second

half of the clock signal. Figure 29.6

297

CS302 - Digital Logic & Design

Figure 29.6

74x163 Counter output Decoded using a 3 x 8, 74x138 Decoder

Figure 29.7

74x138 Decoder enabled by a clock signal

Counter Applications

1. Digital Clock

The primary use of counter is in counting applications and sequencing through a set of

operations. A digital clock can be implemented using the AC 50 Hz frequency as the clock

signal. Figure 29.8

In the digital clock circuit the 50 Hz, 220 volt ac mains sinusoidal signal is shaped into

a 50 Hz, 5 volt square-wave signal. A divide-by-50 counter divides the input 50 Hz signal to a

1 Hz signal. The Seconds, divide-by-60 counter counts up to sixty seconds (0 to 59). The

Minutes, divide-by-60 counter also counts up to sixty minutes (0-59). The Hours, decade

counter counts from 0 to 9. The flip-flop connected to the output of the decade counter is set to

0 or 1 to represent hours from 0 to 9 and 10 to 12 respectively.

298

CS302 - Digital Logic & Design

Figure 29.8

Digital Clock Circuit

The circuit diagram of the Divide by 60 Seconds and Minutes counter is shown in figure

29.9. The 74HC160A decade counter is sued which has Asynchronous clear. The divide by 60

counter is implemented by cascading two 74HC160A counters. The least significant counter

which is the units counter is configured as a decade counter and counts from 0000 to 1001.

On reaching the terminal count value, the RCO output of the Units counter is set to high which

enables the tens counter. The tens counter is configured as a Mod-6 counter, thus it counts

from 000 to 101. The NAND gate output is set to low when the counter counts up to 110, the

NAND gate output is connected to the asynchronous clear input which resets the counter to

000. When the tens counter reaches its terminal count 101, and the units counter reaches its

terminal count 1001, the AND gate output is set to logic high to indicate the terminal count 59

of the divide by 60 counter. The output of the AND gate is connected to the counter enable

pins ENT and ENP of the next stage, thus on reaching the terminal count the next stage is

enabled and the count is incremented by 1 on a clock transition.

The hours counter is implemented using a single decade counter and a flip-flop. Two

counters are not required as the hours counter counts 12 unique output states. Implementation

of a Mod-12 requires 5 flip-flops. Figure 29.10

299

CS302 - Digital Logic & Design

CLR

Figure 29.9

Divide by 60 Minutes and Seconds counter

Figure 29.10a Hours Counter Circuit

The hours unit counter circuit is configured as a decade counter, counting from 0000 to

1001 when it is enabled by the Minutes counter circuit. The terminal count 1001 is detected by

the NAND gate (1) which sets the J input of the flip-flop to logic 1. The K input of the flip-flop is

at Logic 0, therefore on a clock transition the JK flip-flop output is set to logic 1 when the units

counter recycles to 0000. The NOT gate connected to the clock input of the J-K flip-flop allows

the J-K flip-flop to trigger when the units counter is triggered to count from 1001 to 0000. The

unit counter counts to 0001 and 0010 to represent hours 11 and 12 respectively along with the

output of the J-K flip-flop which is set to logic 1. On the next clock transition when the units

counter counts to 0011 the NAND gate (2) output set to logic 0 reloads the units counter with

the count value 0001 and the J-K flip-flop toggles to 0 output as its K input which is set to logic

300

CS302 - Digital Logic & Design

LOAD

Figure 29.10b Hours Counter timing diagram

2. Frequency Counter

A frequency counter is used to measure the frequency of an input signal. The basis for

the operation of a frequency counter is counting of the clock pulses in predetermined time

interval. The frequency of periodic signal is the number of cycles in a time period of one

second. The frequency of the unknown signal can be calculated by counting the number of

clock pulses of the unknown signal and dividing the count number by the time interval in which

the clock pulses are counted, Figure 29.11

In the circuit shown, the input signal with unknown frequency is applied at the AND

gate input. The second input of the AND gate is connected to a signal which determines the

sampling interval. The signal is set to logic high at interval t 1 to enable the AND gate allowing

the input signal to be connected to the clock input of the counter circuit. The sampling interval

signal is set to logic low at the end of the sampling interval t 2 to disable the AND gate and

inhibit the counter from counting. Before the counter counts the clock pulses of the input signal

it is reset by activating the Asynchronous input to clear the counter at interval t 0 . At the end of

the sampling interval the counter output is displayed on 7-segment displays.

301

CS302 - Digital Logic & Design

Clear

Input Signal with

unknown frequency

Counter

Sampling

BCD & Segment

Interval

Decoder

Figure 29.11a Frequency Counter Circuit

Figure 29.11b Timing diagram of the Frequency Counter Circuit

The accuracy of the frequency counter depends on the duration of the timing sampling

interval, which must be very accurate. Consider that during a sampling interval of 1 second

4573 clock pulses of the input signal are measured. Thus, the frequency of the unknown signal

is 4573 Hz. If the same input signal is sampled using a 0.1 second sampling interval then

457.3 pulses are counted, which means that either 457 or 458 will be counted depending on

the start of the sampling interval at t 1 . Similarly, if the sampling interval is reduced to 0.01

seconds, the numbers of clock pulses measured are 45.73, which means that either 45 or 46

will be read.

302

CS302 - Digital Logic & Design

Very accurate sampling intervals are implemented using cascaded counter which is

connected to a very accurate timing signal generated by a crystal controlled oscillator (Astable

multi-vibrator). The output timing signal of each cascade section is available at a switch which

is used to select the appropriate timing signal for controlling the sampling interval. The output

of the switch is connected to the clock input of a negative triggered J-K flip-flop, which divides

the input signal by 2. Thus, when the 1 Hz sampling interval is selected, the signal at the

output of the J-K flip-flop has a time period of 2 seconds. Figure 29.12

100

KHz

Pulse

Crystal

Shaper

Oscillator

Div by 10

100

KHz

Divide by

2 output

Figure 29.12 Cascaded Counter circuit for obtaining accurate sampling intervals

The detailed circuit diagram and the timing diagram of the frequency diagram are

shown in figure 29.13. In the timing diagram the Sampling Interval pulse is obtained from the

output of the J-K flip-flop shown in figure 29.8. The duration of the Sampling interval pulse can

be selected through the switch. The sampling interval signal is connected to the input of the 3-

input AND gate and the clock input of the second J-K flip-flop which toggles its output at each

negative transition of the clock. When the output of the second flip-flop changes to logic 1

(interval t 1 ) it triggers the One-Shot which generates a short output pulse which clears the

Counter circuit. At interval t 2 during the positive half of the sampling interval when the output of

the second J-K flip-flop is high the 3-input AND gate is enabled and the input signal with

unknown frequency is applied at the input of the counter, which count the input signal pulses.

At interval t 3 there is negative transition of the sampling signal, which triggers the second flip-

flop changing its output to logic 0. Logic 0 output of the flip-flop disables the 3-input AND gate

inhibiting the counter from counting. The pulses counted by the counter during interval t 2 to t 3

are directly displayed.

303

CS302 - Digital Logic & Design

Input Signal with

unknown frequency

Counter

Sampling

Clear

Interval

BCD & Segment

Decoder

One

Flip-flop

Shot

Figure 29.13a Detailed circuit diagram of a frequency counter

Input

signal

Sampling

Interval

Output of

flip-flop 2

Counter

reset signal

Counter

Input

t 0

t 1

t 2

t 3

t 4

t 5

t 6

t 7

t 8

t 9

Figure 29.13b Timing diagram of the frequency counter circuit

Design of Synchronous Counters

The counters that have been discussed are binary counters that count in a sequence

either upwards or downwards. The count start and end sequence of a counter can also be set

arbitrarily and the counter can then count up or down with in the terminal count limits.

Counters can also be designed that do not count in a sequence, instead they sequence

304

CS302 - Digital Logic & Design

through a set of predefined arbitrary values. Counters can also be implemented using D flip-

flops instead of J-K flip-flops. Counters are sequential circuits which are designed using

standard set of steps.

Sequential Circuit (State Machine)

A general Sequential circuit consists of a combinational circuit and a memory circuit

(flip-flop). In a clocked Sequential circuit the memory element has a clock input. At any given

instant the memory element is in its present state. On a clock transition the output of the

memory element changes to the next state. The next state is determined by the inputs applied

at the memory input at the time of clock transition. The inputs to the memory which allow the

memory to change its state on a clock transition are known as excitation inputs or excitation

variables. The present state of the memory is represented by state variables. The state

variables and the inputs to the sequential circuit determine the sequential circuit output. Figure

29.14

Figure 29.14 Clocked Sequential Circuit Block diagram

Design Procedure

The design procedure is based on a number of steps starting from defining the state

diagram and ending at the implementation of State machine.

1. State Diagram

A sequential circuit (state machine) is described by a state diagram, which shows the

sequence of state through which the sequential circuit progresses when it is clocked. The state

diagram of a 3-bit Synchronous Up-Counter (sequential circuit) is shown in the figure. 28.3

305

CS302 - Digital Logic & Design

Figure 28.3

State diagram of a 3-bit Up-Counter

2. Next-State Table

Once the state diagram of the sequential circuit is defined, a Next-State Table is

derived which lists each present state and the corresponding next state. The next state is the

state to which the sequential circuit switches when a clock transition occurs. Table 28.1

Present State

Next State

Q 2

Q 1

Q 0

Q 2

Q 1

Q 0

Table 28.1

Next-State Table for a 3-bit Up-Counter

3. Flip-flop Transition Table

The Memory element of the Sequential circuit is implemented using flip-flops. The

number of flip-flops used is determined by the total number of states. When there is a clock

transition at the clock input of the flip-flops they change from their present state to the next

state. The Flip-flop transition table lists all the possible flip-flop input combinations which

allows the present state to change to the next state on a clock transition. The flip-flop

transition table is based on the flip-flop used (D, S-R or J-K). Table 28.2

Flip-flop Inputs

Output Transitions

Q t

Q t+1

306

CS302 - Digital Logic & Design

Table 28.2

J-K flip-flop Transition table

4. Karnaugh Maps

For each state variable shown in the Next-State table, the change from present state to

the next state on a clock transition depends upon the J-K inputs. Table 28.3. Considering the

state variable Q 2 , J 2 and K 2 inputs set to 0 and x (don't care) allow Q 2 to change from present

state 0 to next state 0 shown in the first row. Similarly, the state variable Q 0 changes from 1 to

0 when J 0 and K 0 inputs are set at x (don't care) and 1 respectively. The table is completed

using the information in the Next-State table and the J-K flip-flop transition table. The J-K

inputs can be directly mapped to Karnaugh maps. Table 28.4

Present State

Next State

J-K flip-flop inputs

Q 2

Q 1

Q 0

Q 2

Q 1

Q 0

J 2

K 2

J 1

K 1

J 0

K 0

Table 28.3

J-K flip-flop input table

Q 2 Q 1 /Q 0

Table 28.4a

Karnaugh Map for J 2 and K 2 inputs

Q 2 Q 1 /Q 0

Karnaugh Map for J 1 and K 1 inputs

Table 28.4b

Q 2 Q 1 /Q 0

Table 28.4c

Karnaugh Map for J 0 and K 0 inputs

307

CS302 - Digital Logic & Design

5. Logic expressions for Flip-flop Inputs

Simplified expressions for J 2 -K 2 , J 1 -K 1 and J 0 -K 0 are directly obtained from the

Karnaugh maps.

J 2 = Q 1 Q 0

K 2 = Q 1 Q 0

J 1 = Q 0

K 1 = Q 0

J 0 = 1

K 0 = 1

6. Sequential Circuit Implementation

The Boolean expressions obtained in the previous step are implemented using logic

gates. The sequential circuit implemented is shown in figure 28.4.

Q 0

Q 1

Q 2

SET

flip-flop 1

flip-flop 2

flip-flop 3

CLR

CLK

Figure 28.4

Implementation of the Sequential Circuit

Implementing a 3-bit Up/Down Counter

1. State Diagram

The state diagram of a 3-bit Up/Down Synchronous Counter is shown in the figure.

28.5 . X=0 and X =1 indicates that the counter counts up when input X = 0 and it counts down

when X =1.

308

CS302 - Digital Logic & Design

Figure 28.5

State diagram of a 3-bit Up-Counter

2. Next-State Table

The next state is the state to which the sequential circuit switches when a clock

transition occurs. Table 28.5. The next state outputs for X=0 and X=1 are shown separately.

Present State

Next State X=0

Next State X=1

Q 2

Q 1

Q 0

Q 2

Q 1

Q 0

Q 2

Q 1

Q 0

Table 28.5

Next-State Table for a 3-bit Up-Counter

3. Flip-flop Transition Table

The flip-flop transition table is based on the J-K flip-flop. Table 28.6

Flip-flop Inputs

Output Transitions

Q t

Q t+1

Table 28.6

J-K flip-flop Transition table

309

CS302 - Digital Logic & Design

4. Karnaugh Maps

The J-K flip-flop inputs for change in state variables when X=0 and X=1 are shown in

the table 28.7 . The J-K inputs can be directly mapped to 4-Variable Karnaugh maps. Table

28.8.

Present State

Next State X=0

J-K flip-flop inputs

Q 2

Q 1

Q 0

Q 2

Q 1

Q 0

J 2

K 2

J 1

K 1

J 0

K 0

Table 28.7a

J-K flip-flop input table for X=0

Present State

Next State X=1

J-K flip-flop inputs

Q 2

Q 1

Q 0

Q 2

Q 1

Q 0

J 2

K 2

J 1

K 1

J 0

K 0

Table 28.7b

J-K flip-flop input table for X=1

Q 2 Q 1 /Q 0 X

Table 28.8a

Karnaugh Map for J 2 and K 2 inputs

Q 2 Q 1 /Q 0 X

Table 28.8b

Karnaugh Map for J 1 and K 1 inputs

310

CS302 - Digital Logic & Design

Q 2 Q 1 /Q 0 X

Table 28.8c

Karnaugh Map for J 0 and K 0 inputs

5. Logic expressions for Flip-flop Inputs

Simplified expressions for J 2 -K 2 , J 1 -K 1 and J 0 -K 0 are directly obtained from the

Karnaugh maps.

J 2 = Q 1 Q 0 X + Q 1 Q 0 X

K 2 = Q 1 Q 0 X + Q 1 Q 0 X

J 1 = Q 0 X + Q 0 X

K 1 = Q 0 X + Q 0 X

J 0 = 1

K 0 = 1

6. Sequential Circuit Implementation

The Boolean expressions obtained in the previous step are implemented using logic

gates. The sequential circuit implemented is shown in figure 28.6.

X=0 (up)

Q 0

Q 1

Q 2

X=1 (down)

SET

flip-flop 2

flip-flop 1

flip-flop 3

CLR

CLK

Figure 28.6

Implementation of the Sequential Circuit

311

Design a Decade Counter Using T Flip-flops

Source: https://zeepedia.com/read.php?integrated_circuit_up_down_decade_counter_design_and_applications_digital_logic_design&b=9&c=29

Blaze Hisomed

Design a Decade Counter Using T Flip-flops

Postar um comentário for "Design a Decade Counter Using T Flip-flops"